1. Field of the Invention
This invention relates in general to field effect transistors and in particular to a novel field effect transistor.
2. Description of the Prior Art
Field effect transistors with MIS gate arrangements are well known wherein the source and drain regions are spaced a distance apart in the semiconductor body and lateral arrangements next to each other are on a selected surface of a semiconductor body are the preferred arrangement.
So as to achieve a switching speed as fast as possible with field effect transistors of this type, it is conventional to provide channel lengths between the source and drain regions which are short relative to the current path. One method of achieving this has been called the double diffusion process and is described in the publication "Solid State Electronics" published by the Pergamon Press 1968, Vol. 11, page 411-418. In this process, in a first step, diffusion doping is carried out with a doping material which produces a first conductivity type in a semiconductor body. The diffusion is carried out from the exterior through a mask opening into the semiconductor body where the doping material in the semiconductor body also diffuses laterally beyond the boundary of the mask opening. In a second diffusion step, material which produces an opposite conductivity type is diffused through the same mask opening and in this second process step, the lateral diffusion beyond the mask edge in the finished item is less than was achieved for the doping material during the first process step. Charge carriers which drift laterally out of the diffusion zone of the second process step region towards a drain region pass through a short channel zone in which the doping of the opposite conductivity type exists as a result of the first diffusion step.
So-called buried layers and buffer layers are also known from the prior art. These are referred to as buried layers and buffer layers as described, for example, in "Electronics", Vol. 42 1969, pages 74-80. Such layers are used in bipolar transistors to electrically screen regions of a semiconductor body close to the surface from the underlying regions. In a screened region of this type lying close to the surface, a bipolar semiconductor component such as a bipolar transistor is provided. The buried layers extend completely across the entire region occupied by the semiconductor component and this buried layer does not provide a function which directly interacts with the function of the semiconductor component.
Another field effect transistor of the prior art which has a short channel length, is the so-called VMOS transistor such as described in "Electronic Design", Vol. 21, 1975, page No. 304.
German AS No. 2,415,408 describes a semiconductor body in which a layer is arranged and which is somewhat comparable with a buried layer. The applicants of the present invention are the inventors of German AS No. 2,415,408 and this application provides a field effect transistor arrangement with a layer which extends across the entire surface or the entire region of the transistor and which correspondingly across the entire field effect transistor beneath the gate provides a PN junction which has a space charge region which screens the entire overlying field effect transistor from underlying regions both electrically and functionally.